Horizontally Depleted Field Effect Transistor

Background
Metal semiconductor field effect transistors (MESFETs) are attractive for use in high speed, high voltage applications due to the higher carrier mobility in their channels as compared to metal oxide semiconductor FETs. While silicon-on-insulator (SOI) MESFETs are already an industry proven technology, attempts to keep pace with continuously shrinking semiconductor device sizes will prove challenging under current methods of fabrication in light of the resulting reduction in cross sectional area of the active silicon conduction channel. This cross sectional reduction results in reduced drive current and can even limit conduction to a point where it never supersedes the gate current. Because current fabrication techniques only allow for variations of cross sectional area in one of the two possible dimensions, limits in MESFET scalability result. Thus, MESFETs with multi-dimensional cross sectional area dependency are desirable in order to fully capitalize on the advantages of MESFETs for semiconductor device applications.
Invention Description
Researchers at Arizona State University have developed hybrid ME/MO-SFETs using a silicon-on-sapphire commercial process. The unique design and structure of these devices allows for layout variations to change device properties such as threshold voltage and breakdown voltage. This design does not constrict these versatile structures between the silicide gate and the buried oxide as in traditional SOI MESFET devices, but rather, employs conduction channels formed between two silicide blocks to provide two-dimensional cross sectional area variations. The resulting device provides a highly scalable device for use in fully depleted SOI CMOS applications. Meanwhile, using a MOSFET gate stack can further enhance the performance of this device.